Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment

ABSTRACT

In a multi-channel demodulator, a detection-transition sample estimation scheme classified samples as left (L) or right (R) of a reference position within a symbol interval ( 110 ), or before (B) or after (A) a transition between symbols ( 120 ). When a sample is classified as L or B, the classification of the next sample is forced to R or A, respectively. A memory is provided for storing the contents of various registers when switching to processing of a different channel, and for retrieving from the memory stored data corresponding to previous processing of the different channel. Data read from the memory is written to a register downstream of the register from which it was taken when written to the memory. The read cycle of the memory is extended to ensure that a clock is available to load the data from memory into the downstream register after switching to the new channel.

Benefit is claimed under 35 U.S.C. §119 of Provisional Application No.60/026,431, filed on Sep. 20, 1996, which is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to a demodulator for use in anasynchronous satellite communications system. More specifically, thepresent invention relates to a demodulator circuit and method fordetection and transition sample estimation in a shared multi-carrierenvironment.

DESCRIPTION OF RELATED ART

Traditionally, satellites have performed the function of a simplerepeater in the sky. More is recently, new satellite architectures havebeen proposed that require on-board demultiplexing and demodulation offrequency-division multiple access (FDMA) up-link carriers, basebandprocessing, routing, remultiplexing, and remodulation for down-linktransmissions. This on-board baseband signal regeneration providessignificant connectivity and link advantages.

For asynchronous networks, the various carrier up-link transmissions arenot clock-synchronous. When using a block demultiplexer architecture,the samples at the demultiplexer output are timed relative to the clockthat controls the demultiplexer. Therefore, it is not possible tosynchronize the demultiplexer output samples with the symbols of thevarious carriers. On the other hand, the number of samples used in thedemodulator is ordinarily established by the need to sample the carriersignal appearing at the demodulator input at a rate that is a preciseinteger multiple of (e.g. usually twice) the symbol rate. Furthermore,the time phase of these samples must be adjusted to align the samples atthe proper positions in each symbol. To bridge this gap between thedemultiplexer output and the demodulator input, a sample interpolatorhas been typically used. However, the conventional interpolator functionis computationally intensive, thus requiring a substantial amount ofpower.

An improvement was described in a paper published in 1990 by SoheilSayegh entitled “DSM MCD for FUTURE IBS/IDR Services”, SecondInternational Workshop on Digital Signal Processing Techniques Appliedto Space Communications. This paper, incorporated herein by reference,describes the concept of a multi-carrier demodulator (MCD) capable ofhandling asynchronous input samples and not requiring a synchronousnetwork. At the same time, the MCD is reprogrammable from the ground tohandle different frequency plans and carrier data rates. To accomplishthe handling of asynchronous input samples, the MCD incorporates adigital signal processing scheme called Detection/Transition SampleEstimation (DTSE) for demodulating asynchronous samples in a multi-rateenvironment.

DTSE utilizes the value and position of the two samples that bound themid-symbol point to estimate the value of the detection sample, whilethe transition (end-of-symbol) sample is estimated in a similar manner.In the data detection path, an additional stage of inter-symbolinterference removal processing can be added to improve the value of thedetection sample before symbol resolution.

The above-cited paper contemplates the use of a high precision counterto keep track of relative sample position within a symbol, and thensimply classifying each sample as L (left), R (right) or ζ (unused)depending on the position within a symbol. It is a requirement forproper operation of a DTSE system that the first used sample be a left(L) sample and that the sample immediately following be a right (R)sample. However, due to timing corrections which may be made betweensamples, it is possible for the samples to be classified such that thisrequirement is not satisfied, e.g., with two successive samples beingclassified as L or R, an L sample followed by an unused sample, etc.,resulting in faulty operation.

A further problem with prior art in digital processing in general isthat, in operation with multiple channels, there may be a significanttime penalty in storing the register contents for one channel andretrieving from memory the information to be loaded into registers forcontinued processing of the next channel.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention toprovide a demodulator circuit which operates with low power dissipation,and which is not subject to the sample position ambiguity of the priorart.

It is a further object of the present invention to provide a demodulatorcircuit which can more efficiently operate with multiple channels.

The demodulator circuit according to the present invention includes aninitial detection sample estimation circuit which receives the inputdata signal, takes a plurality of samples for each symbol of the inputdata signal and produces an estimated detection sample of the input datasignal based on the plurality of samples, which may optionally bedelivered to an inter-symbol interference (ISI) removal circuit. Alsoincluded in the demodulator circuit is a transition sample estimationcircuit which receives the input data signal, takes a plurality ofsamples for each symbol of the input data signal and produces anestimated transition sample based on the plurality of samples.

The demodulator circuit also includes a clock loop error detection andloop filter circuit which receives the estimated transition sample andproduces an estimated symbol timing correction value. The demodulatorcircuit further includes a relative position value generator circuitwhich produces a plurality of position values representing the positionof each detection and transition sample in a symbol of the input data,the position values being determined in accordance with both theestimated symbol timing correction value produced by the clock looperror detection and loop filter circuit and in accordance with a knowndistance between successive samples.

The demodulator circuit also includes a gate generator circuit whichreceives the plurality of position values and produces timing gatesignals in accordance with a classification scheme. According to thepresent invention, when a sample is classified as being left of themid-point, the next sample is forced to be classified as right of themid-point, regardless of the position count. Similarly, after a samplethat is classified as being before the transition point, the next samplewill always be classified as after the transition point, regardless ofthe position count.

The position values, together with the timing gate signals, are thenused by various circuits of the demodulator circuit in order to controlthe selection of samples.

According to another aspect of the invention, the demodulator circuitmay also be provided with a switching controller circuit which controlsthe demodulator circuit so that a plurality of channels may be processedby the demodulator circuit. According to one aspect of the invention,each of the just-mentioned circuits in the demodulator circuit may beconstituted by a plurality of shared register circuits which eachinclude a register, an output device and a random access memory whichstores data input from the register during a write cycle of the randomaccess memory and outputs data to the output device for processing andstorage in a subsequent register during a read cycle of the randomaccess memory.

The invention is also directed to a method of implementing and operatingthe demodulator described above.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with reference to the followingdescription, appended claims, and accompanying drawings, in which:

FIG. 1 is a block diagram of a multi-carrier demodulator (MCD) accordingto the present invention.

FIG. 2 is a timing diagram showing symbol locations.

FIG. 3A is a block diagram of an initial detection sample estimationcircuit according to the present invention.

FIG. 3B is a block diagram of a detection sample ISI removal circuitaccording to the present invention.

FIG. 3C is a block diagram of a transition sample estimation circuitaccording to the present invention.

FIG. 3D is a block diagram of a clock loop error detection and loopfilter circuit according to the present invention.

FIG. 3E is a block diagram of a P value and gate generator according tothe present invention.

FIG. 4 depicts a clock gate state machine diagram (LR) associated withan MCD which processes 2-3 samples/symbol in accordance with an aspectof the present invention.

FIG. 5 depicts a clock gate state machine diagram (LR) associated withan MCD which processes 2-4 samples/symbol in accordance with anotheraspect of the present invention.

FIG. 6 depicts a read gate state machine diagram according to thepresent invention.

FIG. 7 depicts a read gate timing diagram according to the presentinvention.

FIG. 8 depicts a shared register block diagram according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The demodulator according to the present invention may be implemented asor included within an application specific integrated circuit (ASIC) foruse as a multi-carrier demodulator (MCD) on-board a satellite. However,alternative implementations of the MCD are possible, e.g., as a fieldprogrammable gate array (FPGA) or with discrete hardware, and the devicemay be employed in terrestrial applications as well. The demodulator candemodulate asynchronous samples in a multi-rate environment without theuse of interpolating filters.

The processing scheme can be used with asynchronous samples in the rangeof less than 2 to greater than 4 complex samples/symbol in a multi-rateenvironment of less than 64 kbits/s to greater than 25 Mbits/s. Theinventive MCD may be made to operate in continuous or burst modequadriphase-shift keying (QPSK), binary phase-shift keying (BPSK) orother modulation techniques. The inventive MCD also implements an alldigital realization of carrier and clock synchronization.

The present invention, which incorporates aspects of the preliminaryversion of DTSE discussed in the above-mentioned paper, utilizes thevalue and position of the two samples that bound the mid-symbol point toestimate the value of the detection sample, while the transition(end-of-symbol) sample is estimated in a similar manner. In the datadetection path, an additional stage of inter-symbol interference removalprocessing is added to improve the value of the detection sample beforesymbol resolution.

The DTSE Scheme and Its Implementation

In FIG. 1, which shows a block diagram of the MCD of the presentinvention, a demultiplexed carrier signal associated with a specificchannel, together with carrier signals for other channels, is input to adigital carrier phase rotator circuit 100 in a time domain multiplexedfashion. The output of the carrier phase rotator circuit 100, whichrepresents the phase and level corrected in-phase (I) and quadrature (Q)components of the input data signal, is passed to the initial detectionsample estimation circuit 110 and the transition sample estimationcircuit 120, which are both part of the above-mentioned DTSE scheme.

Estimated in-phase and quadrature components associated with detectionsamples of the data input are output by the initial detection sampleestimation circuit 110 to a carrier phase tracking circuit 130. Thecarrier phase tracking circuit 130 outputs a phase error signal in orderto correct the phase of the in-phase and quadrature components of thedata input.

Internally, the carrier phase rotator circuit 100 removes the carrierphase and frequency offsets under the control of the carrier recoveryloop included in the carrier phase tracking circuit 130, as follows.After the input samples are re-clocked, the carrier phase rotatorcircuit 100 performs the following well-known operations in order tofacilitate the correction of the phase of the in-phase and quadraturecomponents of the data input:

I_(k)=I′_(k)* cos θ−Q′_(k)* sin θ, and

Q_(k)=I′_(k)* sin θ+Q′_(k)* cos θ.

By way of example, the carrier phase tracking circuit 130, the AGCtracking circuit 140, and the clock loop error detection and loop filtercircuit 170 may include the second order phase locked loop of the JointEstimation and Detection (JED) demodulation scheme described in detailin U.S. Pat. No. 4,419,759, which is incorporated herein by reference.

An automatic gain control (AGC) tracking circuit 140, which alsoreceives the output of the initial detection sample estimation circuit110, outputs an estimated level error signal which is used to correctthe level of the in-phase and quadrature components of the data input.By way of example, the AGC tracking circuit 140 can be implemented as adigital first order phase locked loop (PLL).

A quadrature component generator 150 receives the phase error andestimated level error signals output by the carrier phase trackingcircuit 130 and the AGC tracking circuit 140, respectively. Thequadrature component generator 150 computes scaled cosine and sinevalues and outputs them to the carrier phase rotator 100. The output ofthe carrier phase rotator 100 reflects the phase and level adjustmentsgenerated by the quadrature component generator 150.

The in-phase and quadrature components of the estimated detectionsamples are also output from the initial detection sample estimationcircuit 110 to a detection sample inter-symbol interference (ISI)removal circuit 160, which accounts for inter-symbol interference thatadversely affects the values of the estimated detection samplesgenerated by the initial detection sample estimation circuit 110. Theoutput of the detection sample ISI removal circuit 160 corresponds tothe final output of the MCD, the output being the in-phase andquadrature components of multi-bit soft decision output data.

The transition sample estimation circuit 120 outputs estimatedtransition samples to a clock loop error detection and loop filtercircuit 170, which, in turn, outputs an estimated symbol timingcorrection signal which is preferably at least 14 bits precision. Theoutput of the clock loop error detection and loop filter circuit 170 isreceived by a P value and gate generator 180 which uses the estimatedsymbol timing correction signal to correct a free running P value. Thiscorrected P value reflects the relative position of a sample in asymbol. The P value and gate generator 180 also receives an externallygenerated signal dP. The signal dP represents the expected distancebetween successive samples, i.e., the relative positioning of P valueswith respect to each other. Each P value associated with a sample willbe spaced from the P value of the previous sample by an amountcorresponding to the signal dP as adjusted by the timing correctionsignal.

An externally generated signal, CASE, provides information as to therange of samples per symbol in which the device is operating. The signalCASE is received by the initial detection sample estimation circuit 110,the detection sample ISI removal circuit 160 and the transition sampleestimation circuit 120.

The output of the P value and gate generator 180 includes P values andtiming gate signals which are received by both registers and look-uptables. The timing gate signals determine whether symbols will beprocessed or ignored by the processing elements of the MCD of thepresent invention. Advantageously, the present invention includesinternally closed carrier and clock loops, which eliminates the need forexternal voltage controlled oscillators (VCOs) or numerically controlledoscillators (NCOs).

The initial detection sample estimation circuit 110, the detectionsample ISI removal circuit 160, the transition sample estimation circuit120, and the P value and gate generator 180 implement the DTSE schemementioned above, improved in accordance with the present invention. TheDTSE scheme, which relies on the use of the demodulation techniquesdiscussed below, is an alternative to a conventional interpolatingfilter, and allows the MCD to operate directly on a non-integer numberof samples per symbol.

FIG. 2 depicts one example of a time diagram showing the availablesample locations, the mid-symbol sample location, and the symbol-edgesample locations associated with a specific symbol. The time diagram ofFIG. 2 is for 2.718 samples per symbol which corresponds to about a36.8% symbol separation between samples. An accumulator within the Pvalue and gate generator 180 (FIG. 1) keeps track of the relative sampleposition P within a symbol. Corrections to the accumulator are providedat regular intervals from the clock loop error detection and loop filtercircuit 170 of FIG. 1.

In the example of FIG. 2, the symbol period is taken as one unit and thesample locations within a symbol are expressed in FIG. 2 as a percentageof a symbol which corresponds to a P value. Thus, for example, themid-symbol sample has a P value of 50. For detection purposes, thesamples are classified as L (Left of center), R (Right of center) and z(not used). The samples denoted z are the ones that are far from themid-point of a symbol. Clearly, there is little loss in performance innot including the z samples in the detection scheme because they are atthe symbol edges. Once a sample position P is known, the sample can beclassified as an L, R, or z, subject to the control of the Clock GateState Machine and P Delay chain discussed below which are included inthe P value and gate generator 180.

By way of example, a P value falling between 0 and 12, inclusive, may beclassified as a z. A P value falling between 13 and 49, inclusive, maybe classified as an L. The subsequent sample is then classified as R bythe clock gate state machine.

It is important to note that a determination as to how a P value isclassified is subject to the output of the above-mentioned Clock GateState Machine and P Delay chain. If P values were assigned solely on thebasis of their position within a range of values, without any furtherconsiderations, then the circuit may not operate properly. For example,the MCD would not operate properly if two adjacent samples wereclassified as being left of center. Other mis-classifications may alsooccur. The Clock Gate State Machine and P Delay chain ensures that theMCD classifies samples properly.

For clock tracking purposes, the transition samples are classified as“A” (After symbol edge), “B” (Before symbol edge) or “x” (not used).Samples which are classified as A or B are used to obtain a roughindication of zero crossings. Referring to FIG. 2, once a sampleposition P is known, the sample can be classified as A, B, or x, againsubject to the control of the Clock Gate State Machine and P Delay chainincluded in the P value and gate generator 180. By way of example, a Pvalue falling between 0 and 37 will be classified as A. A P valuefalling between 38 and 62, inclusive, may be classified as x, whereas aP value falling between 63 and 99, inclusive, may be classified as B.However, as noted above, if P values are classified solely based ontheir position within a range of values, the circuit may not operateproperly. The MCD of the present invention utilizes the Clock Gate StateMachine and P Delay chain to ensure the proper classification.

For the purpose of discussing the generation of detection samples, itwill be assumed that proper carrier and clock synchronization trackinghave been carried out. The detection scheme is a two-stage process. Inthe first stage, a preliminary decision is made regarding the value ofthe in-phase and quadrature (I and Q) components of the detectionsamples. This decision is rendered in the initial sample estimationcircuit (element 110 of FIG. 1) and then refined in the second stage.The first stage is necessary due to the use of a non-integer number ofsamples per symbol. In essence, at represents a “simplified”interpolation process.

The internal constitution of the initial sample estimation circuit 110(FIG. 1) is shown in FIG. 3A. The key shown in FIG. 3A should also beused for FIGS. 3B-3E. Initially, the phase and level corrected in-phaseand quadrature components of the data input from the carrier phaserotator circuit 100 (FIG. 1) are routed through registers 25-28 in orderto compensate for delays in the derivation of the P values for a DSElook-up table (LUT) which is embodied in a 256×8 ROM 300. The 256×8 ROM300 receives as input a P value, the externally generated signal CASE,and an LRS signal output by the P value and gate generator 180 (FIG. 1).The delayed in-phase and quadrature components of the data input arethen applied to multipliers 310 and 320 together with detection sampleestimation (DSE) coefficients output from the 256×8 ROM 300. Thesemultipliers 310 and 320 perform the operations:

t1=I_(kl)*W_(kl), and

t2=I_(kr)*(1−W_(kl))

where t1 and t2 are temporary results, W_(kl) is a coefficient, andI_(kl) and I_(kr) are the left and right in-phase components of thedetection path samples, respectively. The coefficient W_(kl) or(1−W_(kl)) is selected by the LRS input to the 256×8 ROM which tells theLUT whether the L or R sample is at the multiplier input. The sameoperation is performed for the quadrature components of the L and Rdetection path sample. The coefficients W_(kl) and (1−W_(kl)) arepreferably determined in accordance with the formulae for W_(l) andW_(r) set forth later herein.

The intermediate results, t1 and t2, for both the in-phase andquadrature components of the detection samples are provided to adders330 and 340. An LR state signal (received from the Clock Gate StateMachine discussed below) resets the adders 330 and 340 at the beginningof each symbol as required to give the correct sum operation. Theoutputs of the adders 330 and 340 are received by registers 31 and 32,with the outputs of the registers 31 and 32 being fed back to the inputof the adders 330 and 340 to form accumulators 331 and 341 which producean initial detection path estimated symbol.

Registers 33 and 34 receive the outputs of the accumulators as inputs,re-clock the results at the symbol rate, and source the data pick-offfor the carrier phase tracking circuit 130 (FIG. 1), the AGC trackingcircuit 140 (FIG. 1) and the detection sample ISI removal circuit 160(FIG. 1).

The second stage of the above-mentioned detection scheme addresses twosources of degradation which result when the detection samples divergefrom the mid-point sample position. These sources of degradation affectthe estimated values of the in-phase and quadrature components of thedetection samples which are output by the initial detection sampleestimation circuit 110 (FIG. 1). One source of degradation isinter-symbol interference (ISI) while the other is a loss of signal tonoise ratio (SNR). The second stage of the detection process isperformed by the detection sample ISI removal circuit 160.

With respect to the loss of SNR which results from the detection schemeof the present invention, consider a single pulse (no ISI) at thereceiver after matched filtering. The matched filter maximizes theoutput SNR at the mid-symbol instant. If the mid-symbol sample value isnot known and only the values and positions within the pulse of samplesL and R are known, then the linear combination of L and R that maximizesthe SNR in the decision is given by:

w₁s(−1)+w_(r)s(r)

where$w_{1} = \frac{{h(l)} - {{h(r)}\quad {h\left( {l + r} \right)}}}{\left\lbrack {1 - {h\left( {l + r} \right)}} \right\rbrack \quad\left\lbrack {{h(l)} + {h(r)}} \right\rbrack}$

and$w_{r} = {{1 - w_{1}} = \frac{{h(r)} - {{h(l)}\quad {h\left( {l + r} \right)}}}{\left\lbrack {1 - {h\left( {l + r} \right)}} \right\rbrack \quad\left\lbrack {{h(l)} + {h(r)}} \right\rbrack}}$

and where h(·) is the impulse response of a raised cosine filter.

The loss in SNR resulting from the use of the L and R samples instead ofthe mid-symbol sample is less than 0.1 dB. Therefore, the main source ofdegradation when using a combination of samples which are not at thedetection point in the actual case of multiple pulse transmission is theISI factor and not the loss of SNR. Accordingly, only a detection sampleISI removal circuit (element 160 of FIG. 1) is included in the MCD ofthe present invention, with no SNR signal loss compensation circuit.Nevertheless, if optimal performance is desired, a SNR signal losscompensation circuit could be incorporated in the MCD.

In order to improve on the preliminary decisions reached above, it isnecessary to remove the effect of ISI, in particular the ISI due to thetwo neighboring pulses (one on each side). Since the location of the Land R samples within the adjacent pulses are known, the magnitude of ISIat the L or R sample due to any pulse can be easily computed. Once thepolarity of that pulse is estimated, the value (magnitude and sign) ofits ISI contribution to the L and R samples can be easily found.

By way of example, the preliminary estimate of the n^(th) detectionsample Ŝ_(p)(n) is revised, and a new estimate Ŝ(n) is computed asfollows:

Ŝ(n)=Ŝ_(p)(n)−D_(p)(n−1)|ISI(n−1, p_(n))|−D_(p)(n+1)|ISI(n+1,p_(n))|

where D_(p)(n) is the polarity of Ŝ_(p)(n), |ISI(n−1,p_(n))| is themagnitude of the ISI contribution to Ŝ_(p)(n) from the proceedingsymbol, and |ISI(n+1,p_(n))| is the magnitude of the ISI contribution toŜ_(p)(n) from the next symbol.

The MCD of the present invention operates in an asynchronous system, inwhich the phase error estimate must be determined using the estimatedin-phase and quadrature components of the detection samples.

Although FIG. 1 shows the output of the initial detection sampleestimation circuit 110 (FIG. 1) being used to obtain a phase errorestimate, the output of the detection sample ISI removal circuit 160 maybe used instead. The estimated or ISI corrected in-phase and quadraturecomponents of the detection samples both provide adequate results whenestimating phase errors. The advantage in using the estimated in-phaseand quadrature components of the detection sample is that the phaseerror estimate can be determined faster and the loops will be morestable, whereas the advantage of using the ISI corrected in-phase andquadrature components of the detection sample is that reduced noise ispresent in the estimated values so that the resulting phase errors aremore accurate. Simulation results show that the rms jitter is almostidentical in both cases.

FIG. 3B shows the internal constitution of the detection sample ISIremoval circuit of FIG. 1 which embodies the second stage of theabove-mentioned detection scheme. Registers 35 and 36 receive theestimated in-phase and quadrature components of the detection samples(i.e. the next symbols I_(k) and Q_(k)) and output the current symbolsI_(k−1) and Q_(k−1) to the registers 37 and 38, which, in turn, outputthe previous symbols I_(k−2) and Q_(k−2).

The outputs of the registers 37 and 38 are received by 256×8 ROMs 345and 350, respectively. The 256×8 ROMs 345 and 350 also receive theinputs (i.e. the next symbols I_(k) and Q_(k)) of the registers 35 and36, respectively. Finally, P values are also input to the 256×8 ROMS 345and 350 along with the externally generated signal CASE. The P valuesare generated by the P value and gate generator 180 of FIG. 1 in themanner discussed below.

The symbols I_(k−2), I_(k), Q_(k−2) and Q_(k) are used to address ISIlook-up tables (LUTs) stored in the 256×8 ROMs 345 and 350. The ISI LUThas an offset compensation factor built in, to make up for the neteffects of the offsets resulting from certain truncation operations andarithmetic compromises in the detection path. Those skilled in the artwill appreciate that standard logic gates may also be configured bysynthesis to perform the equivalent functions of the ISI look-up tablesso that no ROMs are required.

The outputs of the 256×8 ROMs 345 and 350 are received by adders 355 and360 which also receive the output of the registers 35 and 36,respectively. The outputs of the adders 355 and 360 are received byregisters 39 and 40, respectively. The registers 39 and 40 merelyre-clock the in-phase and quadrature components of the multi-bit softdecision output data at a predetermined symbol rate for delivery to theoutside world.

The ROM 300 provides a coefficient output in accordance with the P valueof the left sample and the CASE variable C. Alternatively, the addressinput could be four bits for a left sample P value and four bits for aright sample P value, for a total of 8 bits, and such an implementationis contemplated as an alternative within the scope of the presentinvention. However, as another alternative, since the position of theright sample could be determined by adding to the left sample P valuethe distance between successive samples, the address could instead be aconcatenation of the left sample P value and the inter-sample distancedP. In the preferred embodiment, the CASE variable C is used instead ofthe inter-sample distance dP.

The present inventor has found that the performance of the MCD is notvery sensitive to the precision of the value of the externally generatedsignal CASE. Thus, the signal CASE is represented in only 3 bits. Thereduced number of bits allocated for the signal CASE cuts the size ofthe LUT in half, compared to the use of four bits which would benecessary if a separate P value where used for the right sample R.

If the MCD is processing 2 to 3 samples per symbol, then the CASE valuesmay be selected as follows:

sample/symbol CASE (>)2.00-2.15 7 2.15-2.25 6 2.25-2.35 5 2.35-2.45 42.45-2.55 3 2.55-2.65 2 2.65-2.75 1 2.75-(<)3.00 0

However, if the MCD is processing 2 to 4 samples per symbol, then theCASE values are selected as follows:

sample/symbol CASE (>)2.00-2.1 7 2.1-2.3 6 2.3-2.5 5 2.5-2.8 4 2.8-3.1 33.1-3.4 2 3.4-3.8 1 3.8-(<)4.0 0

Other ranges, including numbers of samples per symbol less than 2, arepossible with minor modifications to the CASE tables and state machine.

Data precision is held to 8 bits throughout the detection path while thegain is held to one as well. This is necessary to maintain maximumprecision throughout and to avoid saturation during AGC transients.Eight bit precision was selected on the basis of early simulations asadjusted by considerations regarding AGC and dynamic range.

FIG. 3C depicts the internal constitution of the transition sampleestimation circuit 120 of FIG. 1. The transition sample estimationcircuit shown in FIG. 3C computes the estimated transition sampledescribed above. This step is necessary due to the use of a non-integernumber of samples per symbol.

The theory underlying the design of the transition sample estimationcircuit is as follows. Since the positions of A and B are known quiteaccurately during tracking, then a very crude estimate of E, the valueat the transition, can be readily obtained by assuming that A, B and Efall on a straight line. However, this will produce a biased estimate ofzero crossings, because even in the absence of noise and inter-symbolinterference caused by pulses before N or after N+1, A, B and E do notfall on a straight line. This bias is on the order of 2% of a symbolinterval. However, it is possible to remove this bias since the filtershape is known (and thus the curve on which A, B and E fall in theabsence of noise and ISI). The hardware implementation of the transitionsample estimation circuit is based upon the straight line approximation.However, it would be a straight forward matter to incorporate theabove-mentioned bias removal.

Initially the phase and level corrected in-phase and quadraturecomponents of the data input from the carrier phase rotator circuit 100of FIG. 1 are routed through registers 41-44 in order to compensate fordelays in the derivation of the P values and passed to a TSE look-uptable which is embodied in a 256×8 ROM 365. Registers 41-44 must beduplicated since they are gated with the BA gate instead of the LR gateto select the timing path samples instead of the detection path samples.

The delayed in-phase and quadrature components of the data input arethen applied to multipliers 370 and 375 together with TSE coefficientsoutput from the 256×8 ROM 365. These multipliers 370 and 375 perform theoperations:

t1=I_(kb)*A_(kb), and

t2=I_(ka)*(1−A_(kb)),

where t1 and t2 are temporary results, A_(kb) is a coefficient (whereA_(ka)=1−A_(ka)), and I_(kb) and I_(ka) are the in-phase components ofthe before and after transition path samples, respectively. Thecoefficient A_(kb) or (1−A_(kb)) is selected by a BAS signal which isinput to the 256×8 ROM 365. The BAS signal tells the LUT whether the Bor A sample is at the multiplier input. The BA state input is generatedby the P value and gate generator 180, as discussed below. The sameoperations are performed for the quadrature components of the before andafter transition path sample. The coefficients A_(kb) and (1−A_(kb)) canbe calculated based on a simple assumption of a value of −1 a halfsymbol before the transition to +1 at a half symbol after thetransition, or can be adjusted to compensate for the 2% bias discussedabove in manner that will be apparent to those of skill in the art.

The outputs of the multipliers 370 and 375 are fed to adders 380 and390, respectively. The outputs of the adders 380 and 390 are input toregisters 45 and 46, respectively, with the outputs of registers 45 and46 fed back to adders 380 and 390 to form accumulators 381 and 391. Theadders 380 and 390 and the registers 45 and 46 also receive a BA statesignal which is output by the P value and gate generator 180 in themanner discussed below. The outputs of the registers 45 and 46 arereceived by registers 47 and 48 which output an estimated transitionsample EST to the clock loop error detection and loop filter circuit 170of FIG. 1.

The clock loop error detection and loop filter circuit 170 shown in FIG.3D performs a well known differentiation operation with some simplelogic gates 395 and 400 (XOR/0's) for the in-phase and quadraturecomponent of the estimated transition sample. The logic associated withthe in-phase component of the transition sample is derived from thefollowing description:

i_(k) i_(k-1) Output 0 0 0 0 1 ˜input 1 0 input 1 1 0

where i_(k) represents the current in-phase component of the transitionsample, i_(k−1) represents the previously sampled in-phase component ofthe transition sample, and ‘˜’ indicates bit inversion. This method ofnegation introduces a single least significant bit (LSB) error which hasbeen shown by the emulation to be insignificant in this application. Asimilar logic is also employed for the quadrature component of theestimated transition sample.

The result of the operations performed in connection with the in-phaseand quadrature components of the estimated transition sample associatedwith each channel is summed by an adder 405 to produce an error signalΔγ which is stored in register 49. This is then supplied to a symboltiming accumulator 409 which includes an adder 410 and a register 50, toproduce an estimated symbol timing correction signal, PEST.

The symbol timing accumulator completes the front end of the first orderclock recovery loop. This accumulator is 16 bits in size although only14 bits are used at the output. Not shown is a programmable barrelshifter which is represented by the jog in the bus which extends fromthe register 49 and the symbol timing accumulator 409. This barrelshifter sets the gain of the clock loop by scaling the error value fedto the adder. The nominal value for the scaling, which is externally setby factors of two, is 3 bits. Taken together with fixed shifts in thepath, this corresponds to a gain of {fraction (1/16)} and a loopbandwidth of about 64 (Rs/Bl). Note that the loop bandwidth isnormalized by the reduction of the data to about 2 samples/symbol anddoes not need to change significantly from carrier to carrier.

FIG. 3E depicts the internal constitution of the P value and gategenerator 180 of FIG. 1. As noted above, the P value and gate generator180 of FIG. 1 embodies the clock gate state machine and P delay chainwhich together generate the gates necessary to select the appropriatesamples at every stage of processing in the remaining portions of theMCD, thereby closing the clock loop.

A free-running P value generator shown in FIG. 3E is comprised of anadder 415 and a register 2 which receives the output of the adder 415.The adder 415 receives as input the output of the register 2 and theexternally generated signal dP. As noted previously, the value of dP isa function of the number of samples per symbol, and, indirectly, thecarrier bit rate. In the preferred embodiment, as contrasted with the 0to 100 example previously described, dP is computed by the followingformula:

dP=round(16384/# samples/symbol),

where the value 16384 is a function of the fact that dP is representedin 14 bits. In this instance, while 14 bits are preferably used torepresent the signal dP, a larger or smaller number of bits may also beused without departing from the scope of the invention. The externallygenerated signal dP is simply the change in position from one sample tothe next as described in detail in the references.

With respect to the externally generated signal dP, fourteen bitprecision gives settability of 0.006% of a symbol, a value which givesnegligible degradation. In the MCD of the present invention, a symbol isconsidered to run from 0 to 16383, where 8192 represents the detectionpoint, as contrasted with the range of 0 to 100 in the earlier example.The present inventor has discovered that optimum operation is achievedif at least 16383 points are used, and there is no need to use more.

An adder 420 receives the output of the register 2 along with the signalPEST generated by the clock loop error detection and loop filter circuit170 of FIG. 1. Initially, the P value assumes a random value. The timingcorrection signal is introduced in order to account for the fact thatthe estimated transition sample detected by the transition sampleestimation circuit 120 at FIG. 1 may not be located at the actualtransition point between samples. Thus, the sum of the output of thefree running P generator and the timing correction signal generated bythe clock loop error detection and loop filter circuit 170 of FIG. 1yields the exact position or P value for the ‘current’ sample once theclock loop is locked. The current P value is output by a register 4which receives the output of the adder 420.

The current position or P value is applied to the clock gate statemachine 425 and used to determine which samples are Left, Right, Before,and After values and which samples will be discarded. The current Pvalue is also delayed by the P delay chain including registers 5 and12-16 in order to derive the appropriate input values for the look-uptables mentioned above. However, the values in the P chain are treatedas unsigned numbers by the clock gate state machine and for the purposeof selecting LUT addresses.

The precision of registers 2, 4 and 5, and the related adders 415 and420 shown in FIG. 3E are preferably 14 bits, while the registers 12-16of the P delay chain are just wide enough to pass the required precision(generally 4 bits).

The adder 420, included in the free running P generator, rolls over byimplementing modulo arithmetic in order to start each symbol over againnominally at zero (as adjusted by the timing offset from the timingaccumulator).

The clock gate state machine 425 is designed to ensure that once asample is selected as L or B, the next sample will always be used for Ror A, respectively. Conventional methods of sample selection, includingthat contemplated in the 1990 paper by Soheil Sayegh, did not alwaysfulfill this requirement.

The clock gate state machine 425 takes as its inputs the current P valueoutput by the register 4 and previous P value from register 5 andproduces the LR and BA gate outputs. As indicated in the key for eachregister shown in FIGS. 3A-3E (the key is actually only shown in FIG.3A, even though it corresponds to FIGS. 3A-3E), these gates outputLeft-Right sample (LR), Before-After sample (BA), Left-Right symbol(LRS), and Before-After symbol (BAS) control signals. Registers withoutthese designators are un-gated.

The same state machine design, duplicated in hardware, is used for bothLR and BA gate generation, while varying only the inputs. A detaileddescription of the LR state machine follows for a case in which the isMCD is processing 2-3 samples per symbol, while the inputs for the BAmachine are shown thereafter. The inputs to the LR state machineassociated with processing 2-3 samples per symbol are as follows:

XPLR=r4<(8192−dP), and

NewSymLR=r4<r5.

These one-bit signals XPLR and NewSymLR are generated from 14 bitcomparators which are internal to the clock gate state machine 425 (8192is a constant and is hard wired). XPLR indicates a P value that is infront of the actual detection point by a distance of more than ‘dP’ andtherefore will not be used (or, in other words, will be ‘X’ed out),while NewSymLR indicates that a new symbol has begun as indicated by thefact that the current P value is smaller than the previous one.

The state machine specification, shown graphically in FIG. 4, is asfollows:

State XPBL; {See element 500 of FIG. 4}

SampGate=0; {These samples are always ‘X’ed out or are not considered}

SymGate=0; {Machine always falls through here}

State BL; {See element 510 of FIG. 4}

SampGate=1; {These samples are always used}

SymGate=1; {Machine always falls though here}

State AR; {See element 520 of FIG. 4}

SampGate=1; {Need two samples/symbol}

SymGate=0; {But only one symbol per symbol}

if (NewSym && XP) goto XPBL; {Early in new symbol}

if (NewSym && !XP) goto BL; {Later in new symbol}

State XPAR; {Otherwise fall to here, element 530 of FIG. 4}

SampGate=0; {This point is ‘dP’ AFTER the detection point}

SymGate=0; {So neither sample is used}

Go to BL; {Loop to BL—since this sample was not used, next sample mustbe}

where ‘&&’ is a logical AND operation and ‘!’ is logical negation. Inaccordance with the operation of the LR state machine, the correct LRand LRS gates are output by the clock state gate machine 425.

In the BA state machine of the clock gate state machine 425, the inputsare determined as follows:

XPBA=r4<(16384-dP), and

NewSymBA=!(r4<8192).

The symbols XPBA and NewSymBA are used to ensure that the correct BA andBAS gates are generated by a BA state machine designed in the samemanner as the above-mentioned LR state machine.

The clock gate state machine 425 may also be designed to handle from 2to 4 samples per symbol in is accordance with LR state machinespecification provided below. The LR state machine specification for 2-4samples per symbol processing is shown graphically in FIG. 5.

As with the design handling 2-3 samples per symbol, only the LR statemachine will be presented when discussing 2-4 samples per symbolprocessing. The BA state machine duplicates the design of the LR statemachine with the exception of the input thereto.

State XPBL; {element 600 of FIG. 5}

SampGate=0; {These samples are always ‘X’ed out}

SymGate=0; {Machine always falls through here}

State BL; {element 610 of FIG. 5}

SampGate=1; {These samples are always used}

SymGate=1; {Machine always falls through here}

State AR; {element 620 of FIG. 5}

SampGate=1; {Need two samples/symbol}

SymGate=0; {But only one symbol per symbol}

if (NewSym && XP) goto XPBL; {Early in new symbol}

if (NewSym && !XP) goto BL; {Later in new symbol}

State XPAR; {Otherwise fall to here, element 630 of FIG. 6}

SampGate=0; {This point is ‘dP’ AFTER the detection point}

SymGate=0; {So neither sample is used}

if (XP) goto XPBL; {Go to next state as appropriate}

if (!XP) goto BL;

where ‘&&’ is a logical AND operation and ‘!’ is logical negation.

Other versions of state machine design can support other ranges ofsamples per symbol without departing from the spirit and scope of theinvention.

Advantageously, the above described clock gate state machine eliminatesthe need for a VCO or NCO in the clock recovery loop where the originalclock does not have to be recreated. This can result in significant costsavings in high volume applications.

The Sharing Scheme and Its Implementation

Because the MCD must accommodate multiple carriers associated withdifferent channels, it must swap intermediate results associated with aspecific channel from a register to RAM on a channel switch signal.Nearly all of the registers in the device have such a RAM associatedwith them. Due to the complex relationship of sample and symbol clocksfor different data rates, a sophisticated controller and read gate statemachine are required to manage the above-described sharing operation.

This on-chip RAM and control circuitry is embodied in the switchingcontroller 190 and allows the single-chip MCD to demodulate anarbitrarily large number of QPSK continuous mode channels in a timeshared fashion. In addition, tri-state outputs can be provided in orderto allow multiple chips to be shared in order to handle still morechannels and to provide for redundancy, while soft decision outputs canbe provided which allow for the use of external Viterbi decoders. Theoperation of the switching controller 190 will be described in greaterdetail below.

Although not explicitly shown in FIGS. 3A-3E, additional circuitry wouldbe necessary to allow the demodulator hardware to handle a large number(e.g., up to 24) of carriers in a time shared fashion. This circuitryconsists mainly of a number of, e.g., 24-word deep memories attached toalmost every register in the device (indicated by the key shown in FIGS.3A-3E) and the state machine to sequence the memory reads and writes atchannel switch time. This process is controlled by the switchingcontroller 190 (FIG. 1), is orthogonal to the demodulation process andis shown in a separate block diagram and discussed at length below,including a detailed description of the shared register design andrequisite state machines.

The switching controller 190 receives externally generated controlinputs or signals, block sync (BS) and switch (SW). Internally, theswitching controller 190 includes a channel address counter (not shown)and four read gate state machines (RGSMs) (not shown). Switchingcontroller 190 produces outputs to control reading, writing andaddressing of the shared registers.

The channel address counter included in the switching controller 190 issimply cleared by BS and incremented by SW. This sequences the addressapplied to the shared registers when the MCD is operating in non-DCS(dynamic channel switching) mode. When the MCD is operating in DCS mode,the channel address is supplied externally.

The read gate state machines are required because, whenever a channelprocessing slot begins in shared mode, it is necessary not only to readthe RAMs associated with the shared registers but also to hold the RAMsin read mode until their outputs can be clocked into the next stage. Inother words, the simplest case would be to write the last value fromchannel N-1 during the last clock time of channel N-1 and to read thestored value for channel N during the first clock time of channel N.However, due to the fact that the clocks are gated by LR, LRS, BA, BAS,and, indirectly, DV (a “data valid” signal of a type commonly used), itwill often be the case that the clock is inactive during the first,second, or even the third nominal clock time after switching. In thesecases, it is necessary to extend the read gate until the first clock inthe next (downstream) stage occurs.

In order to achieve the above-mentioned extension, four read gate statemachines are required. One of each read gate state machine is providedfor LR, LRS, BA, and BAS. In addition, each read gate state machinetakes as inputs the respective clock gate and the switch signal andoutputs the related read gate signal. Only one RGSM will be describedsince they are duplicated four times, with only their inputs and outputsdiffering in each case.

Each read gate state machine uses a truth table implementation toestablish the state sequence. The logic realization of the truth tableis combined with a simple register to complete the implementation.However, the switching controller 190 is not itself shared. An exemplarystate diagram embodying the operation of each read gate state machine isshown is shown in FIG. 6 (expressions followed by an asterisk are merelyincluded for completeness). Each gate signal, LR, LRS, BA and BAS, isactive low. In normal operation, if the gate signal is low, it stays lowuntil GIN (gate in) goes high. However, if the gate signal is high, itstays high until SW goes low. A clear always sets the gate to low(enabled).

By operating in conformity with the state machine diagram shown in FIG.6, the switching controller 190 is able to hold the read gate low untilthe clock has been enabled for the gate in question. By way of example,FIG. 7 shows that a BARd signal (or BA read pulse) goes high one cycleafter a BA signal goes high, while an LRRd signal does the same.However, observe that the BASRd signal goes high one cycle later, onlyafter a BAS signal has gone high, and the LRSRd signal goes high stillanother cycle later to reflect the even longer delay in the LRS signal.

Ungated, but shared, registers are supplied with a switch (SW) signaldelayed by one, which is, in effect, a read gate that is always oneclock period long. The operation of the read gate at the destination isdiscussed below in conjunction with the shared register. All sharedregisters are passed the SW signal as the write strobe.

In DCS mode, the channel address is supplied by an external controllerinstead of the internal counter. Delays are matched to keep everythinglined up. The SW signal is still supplied to the sharing controller toinitiate reads and writes, however the generation of the WR strobe isinhibited when the chip is not selected (by RS, also generated by theexternal controller) to prevent the overwriting of data for channels ofthe same address that are being accessed on some other chip.

RS also controls tri-stating the outputs to allow sharing of ASICs inthe mid band. Finally, RS forces DV low to disable clocking on the chipsthat are not being used to reduce power consumption to minimal levels.

The shared register is the heart of the multi-carrier capability of theMCD of the present invention. As shown in FIG. 8, which is onenon-limiting example of a suitable implementation, the shared register700 may be implemented as four 8-bit registers 705-708 with a 24-by-32bit RAM 710 attached thereto. In addition to the registers 705-708 andthe RAM 710, the shared register 700 includes four multiplexers 715-718and two AND logic gates 720 and 725. All but one of the shared registersin the MCD are set up to allow use as four separate 8-bit registers,while one is modified to be used in the carrier loop as two separateregisters, one of 14 bits, and the other of 18 bits. The 32-bit-wideoverall organization is dictated by efficiency of RAM utilization. Using8-bit-wide RAMs would have resulted in unnecessary duplication ofdecoding circuitry and inefficient placement of the RAMs on the die,considering the fact that all RAMs must be placed around the peripheryof the chip. RAMs larger than 32 bits wide might possibly have been moreefficient, however they were not supported by the ASIC vendor memorycompiler.

In normal operation, all of the registers 705-708 of the shared register700 act as ordinary latches when an input ‘a’ of the correspondingmultiplexer 715-718 is selected. In read mode, input ‘b’ is selected,and the outputs of the RAM 710 are available at the shared registeroutput. In practice, all of the four 8-bit registers 705-708 have theirgates and read inputs separately controlled. This allows them to be usedin different places within modules with different gating requirements.

At write time, the current outputs of the registers are stored in theRAMs. The write enable (WEN) input of the RAM 710 is gated with theclock to ensure that timing requirements are met. The address for theRAMs is the channel ID input (CHID), which selects the appropriatechannel for writing or reading.

The registers are effectively clock gated by the gate input. Thecircuitry shown supports gating by either DV or the LR, BA, LRS, or BASgates. When either of these gate inputs are low, the register holds itscontents constant, effectively freezing operation.

In addition to the applicability in gated clock environments, thisapproach provides another significant advantage. Note that during theread cycle, the output of the RAM 710 is fed forward to the next stagerather than back into the present register. This allows the read cycleto also function as a processing cycle, reducing overhead significantlyin applications with high channel switching rates. This is differentfrom the classic time shared computer equivalent wherein the registersare restored with their original contents before processing resumes,effectively taking at least 2 cycles for every swapping operation (onewrite and one read) rather than one (the write cycle) as in this case.

Although certain preferred embodiments of the present invention havebeen described, various changes and modifications to the disclosedembodiment can be made without departing from the spirit and scope ofthe invention as defined in the appended claims.

What is claimed is:
 1. In an asynchronous communication systemincorporating a detection-transition sample estimation scheme in orderto identify symbols in respective symbol intervals of an input datasignal, a demodulator circuit comprising: an initial detection sampleestimation circuit which receives said input data signal and producesestimated detection samples based on a plurality of samples within eachsymbol interval and in accordance with at least one detection controlsignal; a transition sample estimation circuit which receives said inputdata signal and produces estimated transition samples each based on aplurality of samples of said input data signal in accordance with atleast one transition control signal; and a control signal generator forgenerating said detection and transition control signals in accordancewith classifications of said detection and transition samples as topositions of the detection and transition samples within said symbolintervals, said control signal generator classifying certain of saiddetection samples as being prior to a reference position in a symbolinterval and classifying certain of said detection samples as beingsubsequent to said reference position, and ensuring that every sampleimmediately following a sample classified as prior to said referenceposition is classified as subsequent to said reference position.
 2. Ademodulator in accordance with claim 1, wherein said control signalgenerator classifies certain of said transition samples as being priorto a transition between symbols in said input data signal and certain ofsaid transition samples as being subsequent to a transition betweensymbols in said input data signal, said control signal generatorensuring that every sample immediately following a sample classified asprior to a transition is classified as subsequent to a transition.
 3. Ademodulator according to claim 1, further comprising a clock loop errordetection and loop filter circuit which receives the estimatedtransition samples and produces an estimated symbol timing correctionsignal in accordance with said estimated transition samples and inaccordance with values of previous symbols, and wherein said controlsignal generator produces said detection and transition control signalsin accordance with said estimated symbol timing correction signal.
 4. Ademodulator in accordance with claim 3, wherein said control signalgenerator produces said detection and transition control signals furtherin accordance with an expected distance between successive samples.
 5. Ademodulator in accordance with claim 1, wherein said control signalgenerator generates a first detection control signal to said initialdetection sample estimation circuit representing the position within asymbol interval of one of said samples.
 6. A demodulator in accordancewith claim 5, wherein said first detection control signal represents theposition within said symbol interval of a sample classified as beingprior to said reference position.
 7. A demodulator in accordance withclaim 6, wherein said control signal generator generates a seconddetection control signal to said initial detection sample estimationcircuit representing the position within a symbol interval of a sampleclassified as being subsequent to said reference position.
 8. Ademodulator in accordance with claim 1, wherein said control signalgenerator generates a first transition control signal to said transitionsample estimation circuit representing the position within a symbolinterval of one of said samples.
 9. A demodulator in accordance withclaim 8, wherein said first transition control signal represents theposition within said symbol interval of a sample classified as beingprior to a transition.
 10. A demodulator in accordance with claim 9,wherein said control signal generator generates a second transitioncontrol signal to said transition sample estimation circuit representingthe position within a symbol interval of a sample classified as beingsubsequent to a transition.
 11. A demodulator in accordance with claim5, wherein said detection sample estimation circuit and transitionsample estimation circuit generate their respective estimates further inaccordance with a further control signal representing a number ofsamples per symbol.
 12. A demodulator in accordance with claim 11,wherein said first detection control signal is an n−bit signal and saidfurther control signal is less than n bits.
 13. A demodulator inaccordance with claim 12, wherein said further control signal is n−1bits.
 14. A demodulator in accordance with claim 1, wherein saiddetection and transition control signals include sampling controlsignals for selecting samples for use in producing said estimateddetection and transition samples.
 15. A demodulator circuit inaccordance with claim 1, further comprising an inter-symbol interferenceremoval circuit which receives said estimated detection sample andremoves effects of inter-symbol interference therefrom in order toproduce an inter-symbol interference corrected symbol of said input datasignal which is provided as an output of said demodulator circuit.
 16. Ademodulator circuit in accordance with claim 1, wherein said input datasignal comprises asynchronous input data.
 17. A demodulator circuit inaccordance with claim 14, wherein said initial detection sampleestimation circuit discards samples that are located more than apredetermined distance from said reference position.
 18. A demodulatorcircuit in accordance with claim 14, wherein said transition sampleestimation circuit discards samples that are located more than apredetermined distance from an expected transition location.
 19. Ademodulator circuit in accordance with claim 1, wherein each saiddetection sample estimation circuit and transition sample estimationcircuit comprises: a first register for data being processed; a secondregister downstream of said first register in a signal processing path;a random access memory (RAM) having an input connected to an output ofsaid first register; and a selection circuit receiving as inputs saidfirst register output and an output of said RAM, and responsive to acontrol signal for selecting one of its inputs as an output to an inputof said second register.
 20. A demodulator in accordance with claim 19,wherein said selector output is loaded into said second register inresponse to a clock signal, data is provided at said output of said RAMduring a read cycle of said RAM, and said read cycle of said RAM isextended until said clock signal occurs.
 21. A demodulator in accordancewith claim 19, wherein said RAM receives as at least a portion of anaddress input a signal representing a respective one of a plurality ofchannels with which said demodulator is operable.
 22. In an asynchronouscommunication system incorporating a detection-transition sampleestimation scheme in order to identify symbols in respective symbolintervals of an input data signal, a demodulation method comprising thesteps of: producing estimated detection samples from said input datasignal based on a plurality of samples within each symbol interval andin accordance with at least one detection control signal; producingestimated transition samples from said input data signal each based on aplurality of samples of said input data signal in accordance with atleast one transition control signal; and generating said detection andtransition control signals in accordance with classifications of saidsamples based on their positions within said symbol intervals, saidgenerating step including the steps of classifying certain of saidsamples as being prior to a reference position in a symbol interval andclassifying certain of said samples as being subsequent to saidreference position, and ensuring that every sample immediately followinga sample classified as prior to said reference position is classified assubsequent to said reference position.
 23. A method in accordance withclaim 22, wherein said step of generating said control signals comprisesclassifying certain of said samples as being prior to a transitionbetween symbols in said input data signal and certain of said samples asbeing subsequent to a transition between symbols in said input datasignal, and ensuring that every sample immediately following a sampleclassified as prior to a transition is classified as subsequent to atransition.
 24. A method in accordance with claim 23, further comprisingthe step of producing an estimated symbol timing correction signal inaccordance with said estimated transition samples and in accordance withvalues of previous symbols, and wherein said generating step comprisesproducing said detection and transition control signals in accordancewith said estimated symbol timing correction signal.
 25. A method inaccordance with claim 24, wherein said generating step comprisesproducing said detection and transition control signals further inaccordance with an expected distance between successive samples.
 26. Amethod in accordance with claim 22, wherein said generating step furthercomprises generating a first detection control signal to said initialdetection sample estimation circuit representing the position within asymbol interval of one of said samples.
 27. A method in accordance withclaim 26, wherein said first detection control signal represents theposition within said symbol interval of a detection sample classified asbeing prior to said reference position.
 28. A method in accordance withclaim 27, wherein said generating step further comprises generating asecond detection control signal to said initial detection sampleestimation circuit representing the position within a symbol interval ofone of said samples classified as being subsequent to said referenceposition.
 29. A method in accordance with claim 22, wherein saidgenerating step comprises generating a first transition control signalto said transition sample estimation circuit representing the positionwithin a symbol interval of one of said samples.
 30. A method inaccordance with claim 29, wherein said first transition control signalrepresents the position within said symbol interval of a sampleclassified as being prior to a transition.
 31. A method in accordancewith claim 30, wherein said generating step comprises generating asecond transition control signal to said transition sample estimationcircuit representing the position within a symbol interval of one ofsaid samples classified as being subsequent to a transition.
 32. Amethod in accordance with claim 26, wherein said steps of producing saidestimated detection and transition samples comprise generating saidestimated transition and detection samples in accordance with a furthercontrol signal representing a number of samples per symbol.
 33. A methodin accordance with claim 32, wherein said first detection control signalis an n−bit signal and said further control signal is less than n bits.34. A method in accordance with claim 33, wherein said further controlsignal is n−1 bits.
 35. A method in accordance with claim 22, whereinsaid detection and transition control signals include sampling controlsignals for selecting samples for use in producing said estimateddetection and transition samples.
 36. A method in accordance with claim22, further comprising the step of removing effects of inter-symbolinterference from said estimated detection sample in order to produce aninter-symbol interference corrected symbol of said input data signalwhich is provided as an output of said demodulator circuit.
 37. A methodin accordance with claim 22, wherein said input data signal comprisesasynchronous input data.
 38. A method in accordance with claim 35,wherein said step of producing said estimated detection samplescomprises discarding samples that are located more than a predetermineddistance from said reference position.
 39. A method in accordance withclaim 35, wherein said step of producing said estimated transitionsamples comprises discarding samples that are located more than apredetermined distance from an expected transition location.
 40. Amethod in accordance with claim 22, further comprising the steps of:storing data in a first register data being processed related to a firstchannel; storing said first data in a random access memory (RAM);connecting an output of said RAM and an output of said first register inparallel to inputs of a selection circuit; and selecting one of saidselection circuit inputs for loading to a second register downstream ofsaid first register in a signal processing path.
 41. A method inaccordance with claim 40, wherein said selection circuit output isloaded into said second register in response to a clock signal, and datais provided at said output of said RAM during a read cycle of said RAM,said method further comprising extending said read cycle of said RAMuntil said clock signal occurs.
 42. A method in accordance with claim40, wherein said RAM receives as at least a portion of an address inputa signal representing a respective one of a plurality of channels withwhich said demodulator is operable.
 43. A circuit for performing signalprocessing on a plurality of different signals in an interleaved manner,comprising: a first register for storing data being processed from oneof said signals; a second register downstream of said first register ina signal processing path; a random access memory (RAM) having an inputcoupled to an output of said first register; and a selection circuit forselecting one of said outputs of said first register and RAM for loadingto said second register.
 44. A circuit in accordance with claim 43,wherein said selection circuit output is loaded into said secondregister in response to a clock signal, data is provided at said outputof said RAM during a read cycle of said RAM, and said read cycle of saidRAM is extended until said clock signal occurs.
 45. A circuit inaccordance with claim 43, wherein said RAM receives as at least aportion of an address input a signal representing a respective one ofsaid plurality of signals.
 46. A method of performing signal processingon a plurality of different signals in an interleaved manner,comprising: storing in a first register data being processed from one ofsaid signals; storing in a random access memory (RAM) data from saidfirst register; providing outputs from said first register and RAM incommon to inputs of a selection circuit; and selecting one of saidinputs for loading to a second register downstream of said firstregister in a signal processing path.
 47. A method in accordance withclaim 46, wherein said selection circuit output is loaded into saidsecond register in response to a clock signal, and data is provided atsaid output of said RAM during a read cycle of said RAM, said methodfurther comprising extending said read cycle of said RAM until saidclock signal occurs.
 48. A method in accordance with claim 46, whereinsaid RAM receives as at least a portion of an address input a signalrepresenting a respective one of said plurality of signals.